In the design and implementation of the system-on-chip, verification of this link is increasingly important. The proportion of time spent in the verification process is increasing. The main reason is that as the complexity of SOC chips increases, the scale of verification becomes exponential. increase. The era of system-on-chip has arrived, and at the level of abstraction of RTL-level hardware design, it has been unable to cope with the design and verification of millions and millions of gates. According to statistics, in the past two years, the success rate of a filming has been reduced from 50% to 39%. A successful design cannot be reinvested for months of design verification and hundreds of thousands of dollars. This risk has become unacceptable. Therefore, there is a so-called "verification crisis" in design verification [2]. Functional verification has become a bottleneck in the design and development of integrated circuits, which has made the verification method highly valued by people in the industry. Engineers can't be foolproof when designing, so many system behaviors can not guarantee the correctness of the system function through the test file. The system-on-chip (SoC) is a construction technology, mainly composed of a processor (MCU) and some peripheral devices such as a UART, a MAC, a controller, etc. The system structure diagram is shown in FIG. There are many similarities between SoC verification and ASIC verification: First, simulations are performed to check if the design meets the rules and the chip is tested using various methods. However, the verification of SOC is quite special and there are some special challenges. 2.1 Integration The primary focus of the verification SoC is to check the degree of integration between the various components. The underlying assumption underlying this is that each component has completed its own inspection. 2.2. Co-verification of hardware and software The software running in the processor must be associated with the hardware part to verify. Or we should treat the hardware and software as a complete Device Under Test and test the solution involving the combined state of hardware and software. So we need to find a way to test the tests we write and the correlation between hardware and software in the scope of the tests covered. 2.3. IP Core Multiplexing Establish reusable verification components for reusable IP cores. Establishing reusable verification components will present significant challenges, but at the same time it will also lead to greater benefits. SoC represents a very complex system. A typical SoC requires one or more microprocessors and some other components, such as DSP, Memory, and so on. To verify the SoC, you first need to verify the correctness of each component, and then verify the correctness of the connections and communications between the components. The SoC verification problem is actually how to select the appropriate verification tools and integrate them for specific verification tasks. There are many ways to verify, but so far no one method can be very effective on the functional verification of the system chip. In summary, the verification methods so far can be divided into analog, simulation and formal verification [3]. 3.1, simulation verification Simulation verification applies the excitation signal to the design, performs calculations, and observes the output, and determines whether the result is consistent with expectations. Advantages: Simulation verification is a traditional verification method, and it is still the mainstream verification method. Disadvantages: Incompleteness, that can only prove to be wrong but not proof. Therefore, simulations are generally suitable for detecting large and obvious design errors at the early stage of verification, and are difficult to perform complicated and subtle errors. Simulation verification also relies heavily on the selection of test vectors, and choosing test vectors reasonably and fully to achieve high coverage is a difficult task. Since the designer cannot predict all possible modes of error, some of the best coverage metrics have not yet been discovered. Even if a coverage metric is selected, verification time is a bottleneck. 3.2, simulation verification The model is abstracted from the description of the circuit, and then an external stimulus signal or data is applied to the pattern, and by observing the response of the model under the action of an external stimulus signal, it is judged whether the electronic system has reached the design target. The method of simulation is a commonly used method for designing at present. According to different simulation levels, there are different simulation tools. Advantages: simulation is much faster than simulation Disadvantages: expensive and poor flexibility. 3.3, formal verification Formal verification is another verification method that is different from the simulation method for logical design results [4]. In the top-down design process, at each stage and level of design, each level of design is the design of the above level as the design goal, and the structural description of the design results of this level is the design and synthesis process. . Advantages: completeness, can completely determine the correctness of the design. Disadvantages: First, the original design should be model-extracted, which has mathematical skills and experience requirements for users. Moreover, some tools require manual guidance (such as the proof of a theorem), and some tools have state space explosion issues (such as model checking). Types of: (1) Equivalence test [5] It is a mathematical method to verify the equivalence between a reference design and a modified design. (Figure 2) Using the equivalence verification tool, these two designs can be thoroughly tested to ensure that they have the same performance under all possible conditions. Equivalence verification can also be used to verify the equivalence of different RTL or gate-level implementations. From the design flow of the entire digital system, the problem of equivalence is almost present in each of the upper and lower adjacent design levels, as shown in Figure 2. (2) Theorem Proof Technique. Use axioms and proven theorems to prove that the circuit description is correct. These two methods have their own characteristics. The theorem proves that although it can give a definitive answer to the design, due to the knowledge involved in many mathematical inferences, this requires the user to have a strong mathematical foundation. This is also the method. One reason that cannot be promoted. Equivalence verification is a good way to verify whether different stages of design are equivalent to each other. An SOC design is divided into multiple phases, and then the equivalence between the next phase and the previous phase is a correct guarantee of the design. There is no completely effective method for SOC verification. One of the solutions is based on assertion verification (ABV) [6]. It integrates formal methods into traditional simulation processes. An effective method. The design team inserts the design intent (assertion) in the RTL design and simulates it, then uses formal techniques to check for assertions, constraints, and assertions of legitimate interface behavior, and participate in simulations along with other assertions. The result of the assertion check improves the effectiveness of the simulation. Even with traditional simulation verification, assertions can greatly increase the efficiency of the simulation. Assertion-based verification requires the user to write an assertion that asserts the nature of the verification and therefore requires a property description language. For example, logic and timing aspects. This requires finding a language that can implement the above functions as soon as possible. SystemVerilog is produced in this situation and is gradually being accepted by the industry. Formal methods have made considerable progress in recent years, and in particular, equivalence tests have been integrated into the standard verification process. The progress of design and verification methods should be gradual and no revolutionary changes can occur. Therefore, in the foreseeable years, the hybrid verification method should become the mainstream verification method. Verification based on assertion is a feasible way to combine formal verification with traditional simulation verification. The unified design and verification language that supports this approach is SystemVerilog. The language has been supported by many EDA vendors and users and is expected to become popular. Optoelectronic Information Series Photoelectric information series laboratory related equipment Optoelectronic Information Product,Optical Bench Experiments Physics,Optical Devices Physics,Optical Physics Properties Yuheng Optics Co., Ltd.(Changchun) , https://www.yuhengcoder.com
SOC design verification scheme based on system-on-chip
1 Introduction