The essence of the demonstration of Xilinx full programmable devices

At the ECOC2014 exhibition in Cannes, several members of the OIF Physical and Link Layer (PLL) Working Group, including Xilinx, demonstrated multi-company interoperability of the OIF CEI-28G-VSR and CEI-25G-LR interfaces Sex test. The demonstration includes interoperability between fiber and active copper, covering the emerging CFP4 MSA using OIF CEI-25G-LR electrical specifications to long-distance backplanes using OIF CEI-28G-VSR electrical specifications and QSFP28 passive copper cable.

在戛纳ECOC2014上28Gbps和25Gbps的广泛互操作性演示

Demonstrations with Xilinx Full Programmable Devices include:

CFP4100GBASE-LR4/ ER4f Interoperability with CEI-28G-VSR: The Xilinx FPGA driver CEI-28G-VSR designed with the serial IO analyzer IBERT is inserted into a host card of the Finisar CFP4 ER4f module. A JDSU CFP4100GBASE-LR4 module is located at the far end of the link. Each module is interoperated with 100GBASE-LR4 through a 10km long single mode fiber. JDSU's CFP4 module uses a connector from Yamaichi to drive the OIF-28G-VSR to a 100GbE CDR from Inphi to verify the fidelity of the PRBS-31 data mode. Independently, Inphi's 100GbE CDR drives the OIF-28G-VSR to the JDSU CFP4 module, which in turn drives a 40km long single mode fiber. The data received by Finisar's CFP4 ER4f module shows a bit error rate that exceeds this specification (1E-6). Finisar's CFP4 ER4f module drives the CEI-28G-VSR to the Xilinx FPGA and verifies the PRBS-31 data pattern as well.

Backplane Demonstration Using CEI-25G-LR #1: A Xilinx Virtex FPGA UltraScale Drives Four Channel OIF CEI-25G-LR to Generate 100Gbps Operation, Connected via a Molex Reference Backplane, End-to-End at 12.9GHz Loss >25db. Each channel carries a PRBS-31 data pattern at a rate of 25.78125 Gbps. VirtexUltraScale FPGA generates and checks PRBS on-chip.

Using the CEI-25G-LR Backplane Demo #2: A Xilinx Virtex FPGA's UltraScale-driven four-channel CEI-25G-LR is a reference backplane system from TE ConnecTIvity. The backplane system consists of two STRADA Whisper connectors with Semtech's GN2504 quad-timer board at the end, running an error-free PRBS31 data mode at 25.78125 Gbps.

Details of these demonstrations can be found in the OIF White Paper: Multi-vendor interoperability testing of CFP4, QSFP28 and backplanes using the CEI-28G-VSR and CEI-25G-LR interfaces at ECOC2014.

Author: Steve Leibson, Xilinx director of strategic marketing and business planning

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